In the semiconductor industry, there is a trend toward higher device density. In order to achieve such higher density, smaller features are required. Such requirements frequently involve scaling down device geometries to achieve lower fabrication costs, higher device integration density, higher speeds, and better performance. Along with the advantages from geometry size reductions, improvements to semiconductor devices are being made.
The scaling down process entails high resolution photolithographic process. Photolithography process may include techniques pertinent to coating a photoresist layer on a wafer and exposing the wafer to an exposing source. Subsequent to operations of coating and exposing, developer material is applied on the photoresist layer and the wafer is spun to disperse the developer material over the wafer. Thus at least a portion of the photoresist layer, which can be an irradiated portion or a non-irradiated portion, is dissolved by the developer material and thereby removed in order to form a predetermined pattern.